1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus and a control method therefor.
2. Description of the Related Art
Conventionally known as an image sensor used for a solid-state image pickup apparatus is a Complementary Metal Oxide Semiconductor (CMOS) image sensor. Exposure methods for a CMOS image sensor include a rolling shutter system (which is also called a line shutter system) and a global shutter system (which is also called a simultaneous shutter system or lumped shutter system). The rolling shutter system is a system performing a series of image pickup sequence, i.e., reset, exposure and readout, sequentially for each line, which is the most common system among the CMOS image sensors. Meanwhile, the global shutter system is a system resetting, exposing and transferring a charge to shaded nodes, all simultaneously, for all pixels, which is a system capable of a simultaneous exposure for all pixels.
Now a description is of an example configuration of a pixel circuit for a CMOS image sensor adopting each of the systems by referring to FIGS. 1 through 4.
FIG. 1 is a diagram exemplifying a 3Tr type pixel circuit which is a pixel circuit, for one pixel, of a CMOS image sensor adopting a rolling shutter system. As shown in FIG. 1, the 3Tr type pixel circuit comprises a photo diode (called “PD” hereinafter) which is a photoelectric conversion element for generating a charge by being radiated with light, a readout node (called “FD” (FD: Floating Diffusion) hereinafter) constituting a signal readout point (which is also a charge accumulation (i.e., a detection of light) point in this circuit configuration), a reset-use transistor (called “RST-Tr” hereinafter) which is a reset-use element for resetting the FD, an amplification-use transistor (called “SF-Tr” (SF: Source Follower) hereinafter) which is an amplification-use element of which the gate terminal is connected to the FD and a selection use transistor (called “SLCT-Tr” hereinafter) which is a selection-use element for selecting one line from among a plurality of lines commonly connected to each column output of a pixel unit (not shown herein) of the CMOS image sensor. Note that the RST-Tr, SF-Tr and SLCT-Tr are n-channel Metal Oxide Semiconductor (MOS) transistors. Referring to FIG. 1, the VDD indicates the power supply voltage, the SLCT indicates a signal for controlling the SF-Tr, the VR indicates a reset voltage, the RST indicates a signal for controlling the RST-Tr.
In the 3Tr type pixel circuit comprising such a circuit configuration, the terminal of the PD is the same node as the source terminal of the RST-Tr, reaching at the Silicon surface (i.e., the surface of the CMOS image sensor substrate), and therefore it is not possible to structure so as to bury a PD within the Silicon substrate. Consequently, the PD in such a configuration has an important problem of a large dark-current noise caused by a crystallization defect, a large number of which exists on the Silicon surface.
Meanwhile, a readout circuit (not shown herein) of a CMOS image sensor in many cases uses a Correlated Double Sampling (CDS) circuit canceling a noise by reading a signal twice, i.e., at the time of a charge generated by an exposure existing in the FD and that of not existing therein (i.e., at a reset), and subtracting the latter from the former readings when reading out a signal. A CMOS image sensor constituted by the 3Tr type pixel circuit is face with the problem of a reset noise (i.e., a kTC noise) remaining instead of being canceled, although a noise caused by a variation of the SF-Tr elements can be canceled by the aforementioned CDS circuit. The reason is that the process sequence for a consecutive readout of a signal:
(1) at the time of a charge generated by an exposure existing in the FD, and
(2) at the time of a reset
is the (1) followed by (2) after a relatively long exposure time, in which event a kTC noise, which is random time-wise (i.e., no correlation with time), is generated in each of the signals at the time of a reset prior to the exposure and at the time of a reset in the (2) above.
Also, only three transistors are required for the 3Tr type pixel circuit, and therefore an optical reception area of the PD can be made large; the global shutter system, however, cannot be adopted as it is because a charge retention area is not equipped as in a 5Tr type pixel circuit shown in a later described FIG. 4.
FIG. 2 is a diagram exemplifying a 4Tr type pixel circuit which is a pixel circuit, for one pixel, of a CMOS image sensor adopting a rolling shutter system. As shown in FIG. 2, the 4Tr type pixel circuit is configured to add one transfer-use transistor (called “TG-Tr” (TG: Transfer Gate) hereinafter), which is a transfer-use element, to the 3Tr type pixel circuit shown by FIG. 1. Note that the TG-Tr is a transistor for transferring a charge from the PD to FD and is also an n-channel MOS transistor. Also in FIG. 2, the TG is a signal for controlling the TG-Tr. In this circuit configuration, the FD is placed in a different position from the charge accumulation (i.e., a detection of light) point as a result of the TG-Tr being equipped between the PD and FD.
In the 4Tr type pixel circuit comprising such a circuit configuration, the PD is connected to the FD by way of the TG-Tr, the node of the PD is electrically insulated from the Silicon surface if the TG-Tr is controlled to be OFF, hence making it possible to make a structure of burying the PD in the inside of the Silicon substrate. Due to this, the PD in such a structure is not hardly affected by a dark-current noise caused by a crystallization defect, a large number of which exists on a Silicon surface.
In a CMOS image sensor constituted by the 4Tr type pixel circuit, it is possible to cancel not only a noise caused by a variation of elements of the SF-Tr but also a kTC noise by using the CDS circuit. The reason is that the configuration of the 4Tr type pixel circuit
(1) reads a signal at the time of a reset by resetting the FD, followed by
(2) controlling the TG-Tr as ON, transfer a charge generated by an exposure to the FD and read a signal after the transfer,
prior to a signal readout, that is, the sequence of (1) followed by (2), thus carrying out a signal readout at the time of a reset and a signal readout after a charge transfer by one reset.
Meanwhile, the 4Tr type pixel circuit requires no more than four transistors, making it possible to enable the optical reception area size to be a little larger; this configuration as is, however, cannot adopt a global shutter system because a charge retention area is not equipped as in the 5Tr type pixel circuit shown by a later described FIG. 4.
FIG. 3 is a diagram exemplifying a 4Tr-Tr common use type pixel circuit which is a pixel circuit, for two pixels, of a CMOS image sensor adopting a rolling shutter system. As shown in FIG. 3, the 4Tr-Tr common use type pixel circuit is configured to add one PD and one TG-Tr to the 4Tr type pixel circuit shown in FIG. 2. In this circuit configuration, the TG1-Tr is a transistor for transferring a charge from the PD1 to the FD, and the TG2-Tr is a transistor for transferring a charge from the PD2 to the FD. Note that the TG1-Tr and TG2-Tr are both n-channel MOS transistors. Also, referring to FIG. 3, the TG1 is a signal for controlling the TG1-Tr, and the TG2 is a signal for controlling the TG2-Tr.
In the 4Tr-Tr common use type pixel circuit comprising such a circuit configuration, the RST-Tr, SF-Tr, and SLCT-Tr can be commonly used for two pixels, and therefore it is possible to increase the number of saturation charges and sensitivity and improve an S/N ratio because the optical reception area size of the PD can be increased relative to the 4Tr type pixel circuit shown in the above described FIG. 2 in the case of a pixel size being the same. In the case of an optical reception area size being the same, it is possible to reduce a pixel size, thereby making it possible to accomplish a miniaturization and low cost.
As for the 4Tr-Tr common use type pixel circuit, it is possible to make a structure of burying the PD 1 and PD 2 in the inside of a Silicon substrate in the same manner as the 4Tr type pixel circuit shown in FIG. 2, and therefore there is little influence of a dark-current noise caused by a crystallization defect, a large number of which exists on a Silicon surface.
Also, the 4Tr-Tr common use type pixel circuit, as is, cannot adopt a global shutter system because a charge retention area is not equipped as in the 5Tr type pixel circuit shown by a later described FIG. 4.
As such, in the CMOS image sensor of the rolling shutter system described by referring to FIGS. 1 through 3 or other image sensors adopting the rolling shutter system, the exposure timings are different in the top and bottom directions of an image as is apparent from the exposure system, and therefore a problem is that a photographed object is unnaturally distorted when photographing a moving object.
FIG. 4 is a diagram exemplifying a 5Tr type pixel circuit which is a pixel circuit, for one pixel, of a CMOS image sensor adopting a global shutter system. As shown in FIG. 4, the 5Tr type pixel circuit is configured to add one TG-Tr to the 4Tr type pixel circuit shown in FIG. 2. In this circuit configuration, the TG1-Tr transfers a charge from the PD to a charge retention area (called “FD 1” hereinafter), and the TG2-Tr transfers a charge from the FD 1 to a readout node (called “FD 2” hereinafter). Note that the TG1-Tr and TG2-Tr are both n-channel MOS transistors. Also in FIG. 4, the TG1 is a signal for controlling the TG1-Tr and the TG2 is a signal for controlling the TG2-Tr.
In a CMOS image sensor constituted by such configured 5Tr type pixel circuit, a charge is simultaneously transferred from the PD to the FD 1 in all pixel circuit, and therefore the exposure timing is identical for all pixels, hence no distortion of the photographed image occurring even when photographing a moving object.
And in the 5Tr type pixel circuit, the PD is connected to the FD by way of the TG1-Tr and TG2-Tr, and therefore a node of the PD is electrically insulated from the Silicon surface if the TG1-Tr and TG2-Tr are controlled to be OFF, thus enabling a configuration of burying the PD in the inside of the Silicon substrate. Due to this, the PD configured as such is little influenced by a dark-current noise caused by a crystallization defect, a large number of which exists on a Silicon surface.
Meanwhile, the 5Tr type pixel circuit requires five transistors, limiting an expansion of the optical reception area size of the PD; it, however, can adopt either a rolling shutter system or global shutter system since it is equipped with the FD 1 which is a charge retention area.
Incidentally, techniques relating to a conventional solid-state image pickup apparatus include ones noted in Laid-Open Japanese Patent Application Publications No. 07-78954, No. 2003-332546 and No. 2004-14802, for example.
As described above, the CMOS image sensor, as is, constituted by each of the pixel circuits, i.e., 3Tr type, 4Tr type, 4Tr-Tr common use type, cannot adopt a global shutter system, thus precluding an accomplishment of a low noise image pickup element comprising a global shutter function (i.e., a function capable of a simultaneous all pixel exposure).
Although a global shutter function can conceivably be accomplished by adding a mechanical shutter to a CMOS image sensor constituted by each of the pixel circuits, i.e., 3Tr type, 4Tr type, 4Tr-Tr common use type; such a concept, however, is faced with the problems of a cost increase, a larger size, et cetera.
In the meantime, a CMOS image sensor constituted by the 5Tr type pixel circuit can adopt a global shutter system, thereby making it possible to accomplish a global shutter function; it, however, cannot make a pixel size small, thus facing the problems of precluding a miniaturization and a low cost.